This invention relates to the synthesis of clock signals for use in programmable logic devices.
Typically, in a programmable logic device (PLD), several different clock signals are required to sustain operation of the PLD. For example, in high speed serial interface (HSSI) or high speed serial communications (HSSC) applications, the clocking frequency of the transmitted serial data may be too fast for a PLD to perform meaningful operations on the serial data. Therefore, the PLD may utilize slower clocking frequencies to enable the PLD to process the data.
Clock signals can be generated using phase-locked loops (PLLs) and numerically controlled oscillators (NCOs). Because PLLs are implemented on dedicated circuitry, the number of PLLs that can be implemented on the PLD is limited. This limitation may prevent a PLD from generating a requisite number of clocks that may be needed. Another drawback of PLLs is that they can only generate a finite number of clock frequencies because they are limited by the multiply/divide ratio supported by the PLL circuitry.
NCOs are an alternative approach to using PLLs to generate a clock. In general, a NCO generates a sinusoidal waveform in which the most significant bit of the waveform is used as the clock signal. NCOs are created using available logic resources, not dedicated circuitry. Using logic resources, as opposed to dedicated circuitry, provides as many clocks that can be generated based on the available logic resources. However, using logic resources to generate clocks may be problematic because those resources cannot be used elsewhere.
Another drawback of NCOs is that they introduce jitter into the clock signal they produce. Jitter is dependant on the clocking frequency of the clock signal produced by the NCO. More particularly, jitter is inversely proportional to the clock frequency generated by the NCO. Problems with jitter are further exacerbated by the fact that the maximum clocking frequencies used by PLDs is limited to a few hundred megahertz. For example, a NCO generating a clock frequency of 200 MHz introduces about +/−5 nanoseconds of jitter, which is problematic for many systems. Note that PLDs typically do not operate at higher speeds (e.g., clock frequencies on the order of a gigahertz) because of physical limitations in processing data at such higher speeds.
Therefore, in view of the foregoing, it is an object of this invention to provide circuitry that synthesizes a clock signal of a desired frequency with minimal jitter.